Field of the Invention
This invention relates to integrated circuit memory technology, and more particularly, to a sense/output circuit which is designed for use with a memory device, such as an SDRAM (Synchronized Dynamic Random-Access Memory) device, which is capable of switching off some power-consuming circuit components immediately after the requested data output is completed.
Description of the Related Art
SDRAM is a new type of dynamic random access memory (DRAM) that can run at higher clock speeds than conventional DRAMs. Fundamentally, an SDRAM device is coupled with a sense amplifier which is connected to the output bit lines for amplifying the differential data signals representative of data on the bit lines to a detectable level so that the data can be sensed by the external circuitry connected to the SDRAM device.
During each read cycle, the sense amplifier is activated and remains activated until the requested data have been output to the external circuitry. After this, the memory controller switches off the sense amplifier and inactivates the word lines. One drawback to this practice, however, is that it consumes a great deal of power since the sense amplifier and the word lines are powered on all the time during the read cycle and are disabled only after the requested data output is completed.
One solution to the foregoing problem is to switch off the sense amplifier after a preset delay after the sense amplifier is switched on. One drawback to this solution, however, is that the delay is a fixed value independent of the requested data output; and therefore, a suitable delay margin should be added so as to ensure that the power-off is carried out after the requested data output is completed. This delay margin is dependent on various factors, including process parameters, component parameters, and temperature variations. For this reason, the delay margin is usually set to a large value in order to ensure that the sense amplifier will be switched off only after the requested data output is completed. A large delay margin, however, is highly power consumptive and destabilizes the operation of the SDRAM device.
Therefore, there exists a need in the IC industry for a sense/output circuit for use with SDRAM that is capable of keeping track of the data outputting operation so that some power-consuming circuit components can be switched off immediately after the requested data output is completed.